A clock multiplier may be used to increase the frequency of a clock signal. For example, a frequency doubler circuit may generate an output clock transition or edge from both the rising edges and the falling edges of the clock signal, thereby effectively doubling the frequency of the clock signal. For example, FIG. 1A depicts a frequency doubling operation performed by combining a clock signal (X) with a delayed clock signal (XDEL) using XOR logic to generate an output clock signal (X2) having a frequency that is double the frequency of the clock signal X.
Because the rising and falling edges of the output clock signal X2 are generated in response to transitions in the clock signal X and the delayed clock signal XDEL (which is derived from the clock signal X), the duty cycle of the clock signal X may affect the resulting waveform of the output clock signal X2. More specifically, if the duty cycle of the clock signal X is either greater than or less than 50%, then the period of the output clock signal X2, which may be defined as the time interval between successive edges of the same kind, is not constant but oscillates between two values. For example, FIG. 1B depicts a clock signal X′ having a duty cycle that is less than 50%, which in turn results in a delayed clock signal XDEL′ having a duty cycle that is also less than 50%. When the clock signal X′ is combined with the delayed clock signal XDEL′ in an XOR logic gate, the resulting output clock signal X2′ does not have uniformly spaced state transitions or edges, and therefore may not be suitable for use as a clock signal.